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AN-6754A
Design Guideline to Replace SG6742 with FAN6754A
Introduction
FAN6754A is a highly integrated PWM controller featuring green mode, frequency hopping, constant power limit, and a number of protection functions. The green-mode function, burst-mode function, and a low operating current maximize the light-load efficiency so that the power supply can meet stringent standby power regulations. Frequency hopping reduces the Electro-Magnetic Emission (EMI) by spreading the frequency spectrum. The constant-power-limit function minimizes the component stress in abnormal conditions and helps optimize the power stage design. Protection functions such as brownout protection, overload / open-loop protection (OLP), over-voltage protection (OVP), sense pin short-circuit protection (SSCP), and over-temperature protection (OTP) are fully integrated to improve the reliability of the switched-mode power supply without Table 1. Comparison of SG6742 and FAN6754A SG6742
Brownout Protection Line Voltage Compensation for Pulse-byPulse Current Limit (VLimit-L / VLimit-H) Sense Pin Short-Circuit Protection Gate Drive Clamping Voltage FB Impedance (ZFB) Operating Current (IDD_OP) Leading-Edge Blanking Time (tLEB) Soft-Start Maximum Duty Cycle VFB-G/VFB-N for Green Mode VZDC/VZDCR for Burst Mode V No Saw-Limit (0.9V / 0.56V)
SENSE
increasing system cost. This application note explains how to replace PWM controller SG6742 with FAN6754A. These two devices have the same pin configuration and direct replacement can be achieved without PCB layout change. However, functional improvements to the FAN6754A for higher efficiency and better performance requires several external components to be changed accordingly. Table 1 summarizes the difference between these two devices. The pulse-by-pulse current limit threshold voltage is reduced almost by half to reduce the current sensing loss, which results in 0.4~0.5% efficiency improvement. The operating current is also reduced to achieve less than 100mW standby power consumption for most designs. The typical application circuit and internal block diagram are shown in Figure 1 and Figure 2 , respectively.
FAN6754A
Line Sensing Using HV Pin Adjusted by HV Pin (0.46V / 0.39V) V
SENSE
<0.15V Longer than 150s 18V 5K 2.7mA 150ns 5ms 65% 2.4V / 3.0V 1.6V / 1.7V
<0.05V Longer than 120s 13V 15.5K 1.7mA 280ns 8ms 89% 2.3V / 2.8V 2.0V / 2.1V
(c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 * 10/8/10
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AN-6754A
APPLICATION NOTE
Figure 1.
Typical Application
Figure 2.
Internal Block Diagram
(c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 * 10/8/10
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AN-6754A
APPLICATION NOTE
HV Startup Circuit
Figure 3 shows the simplified schematic for the HV startup circuit. When the AC line is applied to the power supply, the internal high-voltage current source charges the hold-up capacitor C1 through startup resistor RHV. As the VDD pin voltage reaches the turn-on threshold VDD-ON, the PWM controller is enabled and starts normal operation. Then the high-voltage current source is switched off and the supply current is drawn from the auxiliary winding of the main transformer, as shown in Figure 3. For better line surge immunity on the HV pin, it is typical to use a HV resistor larger than 150k. When a large C1 capacitor is required for VDD, the HV resistor limits the charging current for the VDD capacitor, increasing the startup time. If a shorter startup time is required, a two-stage VDD capacitor circuit, shown in Figure 3, is recommended.
Under-Voltage Lockout (UVLO)
The FAN6754A has an under-voltage lockout for VDD. Figure 5 shows the turn-on (VDD-ON) and turn-off (VDD-OFF) threshold levels. Note that there is another VDD turn-off level (VDD-OLP) to minimize the power dissipation of the power stage during the overload protection / open-loop protection condition by extending the VDD discharge time. If the output short is overloaded or the feedback loop is opened, the FB voltage remains above VFB-OLP for OLP delay time (tD-OLP) until the protection is triggered. During that time, the MOSFET drain-to-source current reaches its pulse-by-pulse current limit level for every switching cycle, causing a large amount of power dissipation to the switching devices and transformer. With the two-step UVLO mechanism, the average input power during overload or open-loop condition is significantly reduced.
Figure 3.
Startup Circuit
Soft-Start
The FAN6754A has an internal soft-start circuit that progressively increases the pulse-by-pulse current limit level as shown in Figure 4. The built-in soft-start circuit significantly reduces the input current overshoot during startup, which also minimizes output voltage overshoot.
VDD-ON
Figure 5.
UVLO Specification
VDD
VDD-OFF
General UVLO Gate
VLIMIT (V)
0.46
VDD-ON
0.4 0.36 0.28
VDD
VDD-OFF VDD-OLP
Two-Step UVLO
Gate
0.2
Figure 6.
0.1 1 3 4 5 7
Two-Level UVLO
time (ms)
Figure 4.
Pulse-by-Pulse Current Limit Level for Soft-Start
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(c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 * 10/8/10
AN-6754A
APPLICATION NOTE
Green-Mode Operation
The FAN6754A uses feedback voltage (VFB) as an indicator of the output load and modulates the PWM frequency, as shown in Figure 7, such that the switching frequency decreases as load decreases. In heavy-load conditions, the switching frequency is 65KHz. Once VFB decreases below VFB-N (2.8V), the PWM frequency starts to linearly decrease from 65KHz to 22kHz to reduce the switching losses. As VFB decreases below VFB-G (2.3V), the switching frequency is fixed at 22kHz. As VFB decreases below VFB-ZDC (2.0V), the FAN6754A enters burst-mode operation. When VFB drops below VFB-ZDC, the FAN6754A stops switching and the output voltage starts to drop, which causes the feedback voltage to rise. Once VFB rises above VFB-ZDCR, switching resumes. Burst mode alternately enables and disables switching, thereby reducing switching loss in standby mode, as shown in Figure 8.
FB Input
The FAN6754A employs peak-current-mode control as shown in Figure 9. A current-to-voltage conversion is accomplished externally with current-sense resistor RCS.
Figure 9.
Synchronized Slope Compensation
Figure 7.
Frequency Modulation
Figure 10 is a typical feedback circuit mainly consisting of a shunt regulator and an opto-coupler. R1 and R2 form a voltage divider for output voltage regulation. R3 and C1 are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB=10, CFB=1nF) placed between the FB pin and GND pin can increase loop stability substantially. The maximum source current of the FB pin is about 330A (FB through 15k pulled to 5V reference internally). The phototransistor must be capable of sinking this current to pull the FB level down at no-load condition. Rb and the internal FB pull-up resistor determines the gain feedback loop. The internal pull-up resistor in the SG6742 is 5k, but the FAN6754A has a larger pull-up resistor (15k) to reduce power consumption. Therefore, Rb should be three times the original value when a SG6742 design is replaced with the FAN6754A to have the same loop gain. Forcing FB by an external voltage is not recommended.
Figure 10.
Feedback Circuit
Figure 8.
Burst Mode
(c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 * 10/8/10
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AN-6754A
APPLICATION NOTE
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on spike occurs across the sense-resistor, RS in Figure 11, caused by primary-side capacitance and secondary-side rectifier reverse recovery. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period (280ns), the PWM comparator is disabled and cannot switch off the gate driver. Thus, RC filter with a small RC time constant (e.g. 100 + 470pF) is enough for current sensing. A non-inductive resistor for RS is recommended.
as line voltage increases to makes the actual power limit level almost constant over different line voltages within a universal input voltage range, as shown in Figure 13. In the FAN6754A, the peak-current limiting threshold is adjusted by the peak voltage of the HV pin. When the internal circuit detailed in Figure 14 samples the line voltage information, an internal 1.62k resistor is connected to the HV pin to scale down the line voltage by forming a voltage divider with resistor RHV and the internal resistor.
Figure 13.
Universal Line Voltage Compensation for Constant Output Power Limit
AC In
VLimit (V)
RHV
0.46 VIN 0.39
Figure 11.
Turn-On Spike
1.62k GND
Output Driver / Soft Driving
The output stage is a fast totem-pole gate driver capable of directly driving external MOSFETs. An internal Zener diode, shown in Figure 12, clamps the driver voltage under 13V to protect the MOSFET gate from over voltage. With integrating circuits to control the slew rate of the switch turn-on rise time, the external resistor RG may not be necessary to reduce switching noise.
VDD On/Off Logic
Line Sample Circuit
VIN (V) 1V 3V
Figure 14.
HV Sampling Circuit and VLimit Level vs. VIN
Brownout Protection in HV Pin
As shown in Figure 15, the AC line voltage is monitored by the HV pin using a resistor (RHV), a diode (D1), and an internal line voltage sample circuit. Figure 16 shows brownout protection behavior when the circuit uses the halfwave of the AC line input (VHV) at the HV pin. When the VHV is larger than the brown-in detection voltage threshold (VAC-ON) and VDD is higher than VDD-AC, the PWM begins to operate without any debounce time. Meanwhile, the PWM stops operating when VHV is less than the detection voltage threshold (VAC-OFF) for longer than debounce time. The VAC-ON and VAC-OFF are calculated using the following equations:
VAC-ON ( RMS ) = (0.9 x
VAC -OFF (RMS) = (0.81x
13V
RG Gate RS
FAN6754A
Figure 12. Gate Driver
High/Low Line Compensation in HV Pin
The conventional pulse-by-pulse current limiting scheme has a constant threshold for the current-limit comparator, which results in a higher power limit for high line voltage. The FAN6754A has a current-limit threshold that decreases
(c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 * 10/8/10 5
RHV + 1.6 )/ 2 1.6
(1) (2)
RHV + 1.6 ) / 2 or where RHV is in k . 1.6
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AN-6754A
APPLICATION NOTE
VDD Over-Voltage Protection (VDD_OVP)
VDD over-voltage protection protects the VDD pin from damage from over-voltage. The VDD voltage rises when an open-feedback loop failure occurs. Once the VDD voltage exceeds 25V (VDD-OVP) for longer than 165s, the power supply is latched off until VDD is discharged below VDD-LH.
Sense Pin Short-Circuit Protection (SSCP)
This protection is used for Limited Power Source (LPS) safety testing. This test is performed with RSENSE shorted to ground, thus increasing the output power. If the output voltage rating is set to 19V, this protection should be triggered before the output wattage increases to 100W. Figure 18 shows this detection method. When RSENSE is shorted to ground, the FAN6754A detects the voltage on the SENSE pin during the gate's on time. After debounce time, the gate turns off and VDD goes into hiccup mode. The sense resistor short-circuit protection is triggered if all of the following occur: gate is in a HIGH state; and the on-time of gate; tON-SSCP is over 4.4s and VSENCE< 50mV; and
Figure 16. Brownout Protection Behavior
Figure 15.
Brownout Circuit
during the debounce time of 120s, if all pulse conditions are as above or the SSCP counter is reset. Because of the fixed gate's on-time checking, the peak current of the inductor is different between high line and low line. The FAN6754A sets VSENSE detection levels for all input voltage ranges.
Overload / Open-Loop Protection (OLP)
When output is overloaded, the drain current reaches its pulse-by-pulse current limit level, limiting the input power. Then, the output voltage drops and no current flows through the opto-diode, which causes the feedback voltage to increase above the OLP protection threshold (4.6V). A similar response occurs when the feedback loop is open and no current flows through the opto-diode. When the feedback voltage is higher than 4.6V for longer than the OLP delay time, the OLP protection is triggered, as shown in Figure 17.
Figure 18.
SSCP Detection Method
To prevent miss-triggered protection in normal mode (RSENSE not shorted to ground); especially at lower AC line input voltages and light-load conditions, the transformer's inductance should not be too high in inductance. The following is a design example; (1) If the RHV is 200K, the brownout voltage should be 80VAC; assume the ripple is 15V at light-load condition. (2) RSENSE is 0.15, and has 5% tolerance. (3) The minimum specification of tON-SSCP is 4s from the datasheet. (4) The maximum specification of VSSCP-L is 70mV from the datasheet.
Figure 17.
OLP Behavior
(c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 * 10/8/10
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AN-6754A
APPLICATION NOTE
The maximum primary-side inductance of the transformer should be:
Lmax = ( VBrownout _ min ) x t ON - SSCP (min) x R SENSE (min) VSSCP -L(max) =
(3)
VBulk diL (4) = LP dt
( 80 V x 2 - 15 V ) x 4s x 0.1425 = 799H 70mV
In general, the manufacturing tolerance of the transformer has 10%, the system designer should consider this tolerance; don't allow a maximum value over 799H for this case. In the FAN6754A, there are two conditions that trigger SSCP in system applications as show below. (1) Power off on low line input with a heavy load. If power off during a low input voltage line during a heavy load, then the FAN6754A will trigger the SSCP function as shown in 0 and Figure 1. (SSCP function is re-start behavior.)
Figure 21. 11/2 AC Cycle DIP Test
Thermal Protection
A constant current source IRT (100A) is connected to the RT pin for over-temperature protection, (reference Figure 22.) A NTC thermistor RNTC, in series with resistor RA, is typically connected between the RT pin and the GND pin. When VRT is less than 1.035V (VRTTH1) and larger than 0.7V, the PWM is disabled after the debounce time tD-OTP-1. If VRT is less than 0.7V (VRTTH2), the PWM output is latched off after a very short debounce time of tD-OTP-2. This function is used for external protection. If this thermal protection design is not used, connect a small capacitor (around 0.47nF is recommended) between the RT pin and the GND pin to prevent noise interference. The RT capacitor cannot be larger than 1nF or, thermal protection is triggered during startup. If the RT pin is not connected to a NTC resistor to implement over-temperature protection, add an in-series 100K resistor to ground to prevent noise interference. This pin is limited by internal clamping circuit.
9.12ms
Power Off
Figure 19. Power Off on 90VAC with Heavy Load (Zoom Out - Ch1:Sense Ch2: FB Ch3:AC Ch4:Bulk)
120us
< 50mV
Figure 22. Figure 20. Power Off on 90VAC with Heavy Load (Zoom In - Ch1:Sense Ch2: FB Ch3:AC Ch4:Bulk)
Thermal Protection Circuit
Lab Note
Before rework or solder/de-solder on the power supply, discharge the bulk capacitors in the primary side by an external bleeding resistor. Otherwise, the PWM IC may be damaged by external high voltage during solder/de-solder. This device is sensitive to ESD discharge. To improve production yield, the production line should be ESD protected according to ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1.
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(2) During an AC DIP, when the AC DIP cycle is over 30ms (11/2 cycle) for 100% drop. If the bulk voltage slowly droops, the inductor's current slope flattens as shown in Equation 4, this condition triggers the SSCP function. Even when the AC DIP is released, the gate stops going HIGH and VDD restarts again.
(c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 * 10/8/10
AN-6754A
APPLICATION NOTE
Printed Circuit Board (PCB) Layout
High-frequency switching current / voltage makes PCB layout a very important design issue. Good PCB layout minimizes excessive EMI and helps the power supply survive during surge / ESD tests.
Guidelines:
Two suggestions with different pro and cons for ground connections are offered: GND3 2 4 1: This could avoid common impedance interference for sense signal. GND3214: This could be better for ESD testing where the earth ground is not available on the power supply. Regarding the ESD discharge path, the charges go from secondary through the transformer stray capacitance to GND2 first. The charges then go from GND2 to GND1 and back to the mains. Control circuits should not be placed on the discharge path. Point discharge for common choke can decrease highfrequency impedance and increase ESD immunity. Should a Y-cap between primary and secondary be required, connect this Y-cap to the positive terminal of C1. If this Y-cap is connected to the primary GND, it should be connected to the negative terminal of C1 (GND1) directly. Point discharge of this Y-cap helps ESD. However, the creepage between these two pointed ends should be large enough to satisfy the requirements of applicable standards.
To get better EMI performance and reduce line frequency ripples, the output of the bridge rectifier shown in Figure 23 should be connected to capacitor C1 first, then to the switching circuits. The high-frequency current loop is in C1 - Transformer - MOSFET - RS - C1. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 41) short, direct, and wide. High-voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heatsink is used for the MOSFET, connect this heatsink to ground. As indicated by 3, the ground of control circuits should be connected first, then to other circuitry. As indicated by 2, the area enclosed by transformer auxiliary winding, D1, C2, D2, and C3 should also be kept small. Place C3 close to the FAN6754A for good decoupling.
Figure 23.
Layout Considerations
(c) 2010 Fairchild Semiconductor Corporation Rev. 1.0.0 * 10/8/10
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AN-6754A
APPLICATION NOTE
Related Datasheets
FAN6754A -- Highly Integrated Green-Mode PWM Controller (Brownout and Constant Power Limited by HV Pin)
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